Non-volatile memories are widely used in applications where the data stored in the memory device is preserved even in the absence of an electrical supply. Among the types of non-volatile memories, the electrically programmable (and erasable) memories, such as the flash memories, are popular in the applications where the data to be stored is updated with frequency.
In order to be programmed, the cells of a flash type memory may require the application of respective programming pulses at the drain terminals. To be read, the cells instead require that the gate terminals be biased to a respective reading voltage. The voltage value of the programming pulses is typically different from the value of the reading voltage. For example, the programming pulses may be on the order of 4 volts, while the reading voltage may be on the order of 5 volts.
These voltages are typically generated by taking the output voltage of a voltage boost circuit, such as a charge pump, and regulating the value thereof by way of a voltage regulator circuit coupled to the output of the charge pump. Among the various types of voltage regulators, the type more readily employed in this application is the so-called “linear” topology, i.e. based upon a regulation transistor adapted to operate in the linear region for regulating the output voltage to the desired voltage to make the output of the voltage regulator as stable as possible. The regulation transistor is typically driven by a feedback-connected operational amplifier.
In order to optimize the area consumption within the semiconductor material die where the flash memory is integrated, a single voltage regulator is used for generating the required voltages both during the reading operations and the writing operations. The design of a voltage regulator of this type may be problematic, since such a regulator should be capable of rapidly and efficiently compensating for the sudden voltage variations due to abrupt changes of load and current demands during selection of the memory cells for the reading and programming operations.
Specifically, during a programming operation, a group of selected memory cells is biased for receiving a respective programming current, for example, of the order of 60 uA per cell. As soon as the memory cells of the group to be programmed are selected, the current request tends to rapidly decrease the voltage of the output terminal of the voltage regulator. This voltage decrease is compensated by the voltage regulator, which acts by increasing the driving voltage of the regulation voltage. As soon as the memory cells of the group are deselected (when the programming is ended), the current request suddenly expires, and the voltage of the output terminal of the voltage regulator tends to rapidly increase. In this case, the compensation carried out by the voltage regulator provides for reducing the driving voltage of the regulation transistor.
During a reading operation, a group of memory cells is selected for reading of stored data, such selection provides for a rapid increase of the load (for example, of the order of about 500 fF) caused by the coupling with the gate terminals of the memory cells of the group. This increase of the load generates a corresponding increase in the current request, which tends to rapidly lower the voltage in the output terminal of the voltage regulator. In this case as well, the voltage decrease is compensated by the voltage regulator, which operates by increasing the driving voltage of the regulation transistor. As soon as the memory cells of the group are deselected (when the reading is ended), the current request suddenly expires, since the load suddenly decreases, and the voltage of the output terminal of the voltage regulator tends to increase. As a consequence, the compensation carried out by the voltage regulator provides for decreasing the driving voltage of the regulation transistor.
In order to improve the performance of the voltage regulator, both from the response speed point of view and from the stability point of view, different approaches have been disclosed. Particularly, an approach provides for increasing the response speed of the regulator by increasing the response speed of the operational amplifier. However, this approach may be problematic from the electric power consumption point of view, especially in the case wherein the operational amplifier is directly supplied by the charge pump coupled to the regulator itself.
According to another approach, the stability of the voltage regulator is improved by increasing the capacity of the output terminal (of the voltage regulator), for example, through the connection of one or more additional filter capacitors. However, the addition of capacitors may require an excessive waste of area in the semiconductor material die where the flash memory is integrated.
U.S. Pat. No. 5,945,819 discloses a voltage regulator coupled between first and second voltage references and having an output terminal for delivering a regulated output voltage. The voltage regulator includes at least one voltage divider, coupled between the output terminal and the second voltage reference, and a serial output element coupled between the output terminal and the first voltage reference. The voltage divider is coupled to the serial output element by a first conduction path, which includes at least one error amplifier whose output is coupled to at least one driver for turning off the serial output element. The voltage regulator includes, between the voltage divider and the serial output element, at least a second conduction path for turning off the serial output element according to a value of the regulated output voltage in advance of the action of the first conduction path. U.S. Pat. No. 7,714,553 discloses a voltage regulator that includes an under voltage detector having a charge transistor smaller than an output transistor of the voltage regulator, providing a detection path for fast response, and compensating for the under voltage without large control current when loading changes from light to heavy.
U.S. Patent Application Publication No. 2003/098674 discloses a wideband voltage regulator which is configured to provide suppression of fast transients and includes a boosting circuit and a sensing circuit. The boosting circuit can be suitably configured to boost the voltage regulator response, while the sensing circuit can determine when such a boost may be desired. Accordingly, the response of the voltage regulator can be accelerated to a fast load transient beyond the closed loop bandwidth limited response or the slew rate limited response of the voltage regulator. An exemplary voltage regulator can be configured with an active sensing circuit comprising a sensing amplifier with switch control outputs, and a boosting circuit comprising N stored charge sources, e.g. boost capacitors, and (3N−1) switches that are configured to accelerate the voltage regulators response to a fast load transient beyond the closed loop bandwidth limited or slew rate limited response of the voltage regulator.
U.S. Pat. No. 6,157,176 discloses a linear type of voltage regulator having at least one input terminal adapted to receive a supply voltage and one output terminal adapted to deliver a regulated output voltage, a power transistor, and a driver circuit for the transistor. The driver circuit includes an operational amplifier having an input differential stage biased by a bias current, which varies proportionally with the variations of the regulated output voltage at the output terminal of the regulator.
The approaches disclosed in U.S. Pat. Nos. 5,945,819 and 7,714,553 and in U.S. Patent Application Publication No. 2003/098674 are capable of increasing the speed of the voltage regulator only in response to load increases. Employing approaches of this type when the load diminishes (e.g. at the end of a reading operation) may result in the response of the voltage regulator being excessively slow. The approach disclosed in U.S. Pat. No. 6,157,176 may entail a drastic increase in power consumption, in terms of current required by the charge pump.